74LS138 SMD ( DM74LS138M )
9,66 TL
74LS Serisi
74LS139 - Decoders/Demultiplexers
The LS138 decodes one-of-eight lines, based upon the conditions
at the three binary select inputs and the three enable
inputs. Two active-low and one active-high enable inputs reduce
the need for external gates or inverters when expanding.
A 24-line decoder can be implemented with no external
inverters, and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for demultiplexing
applications.
at the three binary select inputs and the three enable
inputs. Two active-low and one active-high enable inputs reduce
the need for external gates or inverters when expanding.
A 24-line decoder can be implemented with no external
inverters, and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for demultiplexing
applications.
Features
Designed specifically for high speed:
Memory decoders
Data transmission systems
Memory decoders
Data transmission systems
LS138 3-to-8-line decoders incorporates 3 enable inputs
to simplify cascading and/or data reception
to simplify cascading and/or data reception
Schottky clamped for high performance
Typical propagation delay (3 levels of logic) 21 ns
Typical propagation delay (3 levels of logic) 21 ns
Typical power dissipation 32 mW
Vcc range : 4,75V - 5,25V
Package : SO16
Package : SO16
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