XC9572 In-System Programmable CPLD
• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1600 usable gates
• Up to 72 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
• Programmable power reduction mode in each macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one XC9500 concurrently
• 44-pin VQFP packages
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