74LS112 ( DM74LS112AN )
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Kategori
Dorukan Stok No
DRK-1048-1
Fiyat
0,65 USD + KDV
Havale
26,11 TL
(%3,00 havale indirimi)
26,92 TL
74LS Serisi
74LS112 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
74LS112 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
This device contains two independent negative-edge-triggered
J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Operating temp. range : 0°C - 70°C
Vcc range : 4,75V - 5,25V
Package : DIP16
Vcc range : 4,75V - 5,25V
Package : DIP16
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